Some integrated CMOS-DMOS technologies include field plate trench DMOS (diffused metal oxide semiconductor) transistors to optimize on resistance. Optimization of field plate trench DMOS devices can be hindered in that the optimum epitaxial doping level for the DMOS transistor is by a factor of 3 to 10 higher than that for a regular well of a CMOS (complimentary metal oxide semiconductor) device for the same voltage class. Also, when integrating an isolated n-well into the technology e.g. for low side logic or isolated vertical bipolar devices, the required epitaxial thickness for the analog part of the technology is typically larger than that for an optimized field plate trench DMOS device (by up to a factor of 2.5). Furthermore, integrated circuit designs which use avalanche clamping instead of active zener devices to reduce the required voltage class of the DMOS device require a higher voltage class for the analog part of the integrated CMOS-DMOS technology compared to the DMOS device. This further increases the need for separate effective epitaxial thicknesses and doping levels for the DMOS devices and analog wells.
Conventional integrated CMOS-DMOS technologies typically use an epitaxial layer mostly defined by the requirements for the analog part of the technology and attempt to adapt the effective epitaxial doping and/or thickness locally for the DMOS part. In one example, an n-buried layer can be used for n-channel DMOS devices to effectively reduce the epitaxial thickness in the DMOS area. Another example involves oxidation enhanced diffusion of the n+ substrate to reduce epitaxial thickness underneath a DMOS device. In either case, only the thickness and doping level of the epitaxial layer close to the substrate can be controlled. A third example involves enhancing the doping of the epitaxial layer in the mesa region between trenches in the DMOS area by an additional high energy implant. This option increases the doping level in the mesa region, but the doping level is not increased by more than a factor of 2. Also, this option is typically limited to the upper part of the mesa region due to the energy limitations of common high energy implanters. Another example reduces the thickness of the epitaxial layer in the DMOS region by removing part of the epitaxial layer. None of these conventional techniques use a stacked or graded epitaxial layer for the DMOS devices and analog wells. Also, none of these conventional techniques address the problem of increased topography which arises due to the removal of material in the DMOS area.
To integrate a state of the art discrete DMOS device into a CMOS-DMOS technology, at least two of the techniques listed above are typically needed which substantially increases cost and process complexity. Also, the implicit limitations of such an approach still do not allow for full optimization of the DMOS device.